10/07 作業

這次比較複雜
module top;

wire A, B, C, D, E, OUT1, OUT2, OUT3, OUT4, OUT5;
system_clock #1600 clock1(A);
system_clock #800 clock2(B);
system_clock #400 clock2(C);
system_clock #200 clock2(D);
system_clock #100 clock2(E);

not a1(OUT1, A);
and a2(OUT2, OUT1, B);
nor a3(OUT3, C, D);
and a4(OUT4, OUT3, E);
or a5(OUT5, OUT2, OUT4);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>3200)$stop;

endmodule