三位元全加器(行為模式)

module fulladder (c_out, sum, a, b, c_in);
wire s1, c1, c2;
output c_out;
output sum;
input a, b, c_in;

assign{c_out,sum}=a+b+c_in;
endmodule

module adder3( c_out, sum, a,  b, c_in);
wire [2:0] c;
output [2:0] sum;
output c_out;
input [2:0] a;
input [2:0] b;
input c_in;

fulladder fa1(c[1], sum[0], a[0], b[0], c_in) ;
fulladder fa2(c[2], sum[1], a[1], b[1], c[1]) ;
fulladder fa3(c_out, sum[2], a[2],b[2], c[2]) ;


endmodule

module main;
reg [2:0] a;
reg [2:0] b;
wire [2:0] sum;
wire c_out;

adder3 DUT (c_out, sum, a, b, 1'b0);

initial
begin
  a = 3'b111;
  b = 3'b000;
end

always #50 begin
  b=b+1;
  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);
end

initial #2000 $finish;

endmodule

三位元全加器(結構模式)

module fulladder (c_out, sum, a, b, c_in);
wire s1, c1, c2;
output c_out;
output sum;

xor g1(s1, a, b);
xor g2(sum, s1, c_in);
and g3(c1, a,b);
and g4(c2, s1, c_in) ;
xor g5(c_out, c2, c1) ;

endmodule

module adder3( c_out, sum, a,  b, c_in);
wire [2:0] c;
output [2:0] sum;
output c_out;
input [2:0] a;
input [2:0] b;
input c_in;

fulladder fa1(c[1], sum[0], a[0], b[0], c_in) ;
fulladder fa2(c[2], sum[1], a[1], b[1], c[1]) ;
fulladder fa3(c_out, sum[2], a[2],b[2], c[2]) ;


endmodule

module main;
reg [2:0] a;
reg [2:0] b;
wire [2:0] sum;
wire c_out;

adder3 DUT (c_out, sum, a, b, 1'b0);

initial
begin
  a = 3'b111;
  b = 3'b000;
end

always #50 begin
  b=b+1;
  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);
end

initial #2000 $finish;

endmodule

一位元全加器(行為模式)

module test_adder1;

 reg a,b;
 reg carry_in ;
 wire sum;
 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial
  begin

    carry_in = 0; a = 0; b = 0;
    # 100 if ( carry_in != 0 | sum !== 0)
                $display(" 0+0+0=00 sum is WRONG!");
              else
                $display(" 0+0+0=00 sum is RIGHT!");
    carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_in != 0 | sum !== 1)
               $display(" 0+0+1=01 sum is WRONG!");
              else
               $display(" 0+0+1=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 0;
    # 100 if ( carry_in != 0 | sum !== 1)
               $display(" 0+1+0=01 sum is WRONG!");
              else
               $display(" 0+1+0=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 1;
    # 100 if ( carry_in != 0 | sum !== 1)
               $display(" 0+1+1=10 sum is WRONG!");
              else
               $display(" 0+1+1=10 sum is RIGHT!");
    carry_in = 1; a = 0; b = 0;
    # 100 if ( carry_in != 0 | sum !== 1)
               $display(" 1+0+0=01 sum is WRONG!");
              else
               $display(" 1+0+0=01 sum is RIGHT!");
    carry_in = 1; a = 0; b = 1;
    # 100 if ( carry_in != 0 | sum !== 1)
               $display(" 1+0+1=10 sum is WRONG!");
              else
               $display(" 1+0+1=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_in != 0 | sum !== 1)
               $display(" 1+1+0=10 sum is WRONG!");
              else
               $display(" 1+1+0=10 sum is RIGHT!");

    carry_in = 1; a = 1; b = 1;
    # 100 if ( carry_in != 1 | sum !== 1)
               $display(" 1+1+1=11 sum is WRONG!");
              else
               $display(" 1+1+1=11 sum is RIGHT!");
    $finish;
  end
endmodule



module adder1_behavorial (carry_out, sum, a, b, carry_in);
 input a, b, carry_in;
 output carry_out, sum;
  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);
  assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule

1位元全加器(結構模式)

module top;

wire A, B, CIN, COUT, SUM, A1, A2, A3, A4, X1;
system_clock #400 clock1(A);
system_clock #200 clock2(B);
system_clock #800 clock2(CIN);
and a3(A3, A, CIN);
and a2(A2, CIN, B);
and a1(A1, A, B);
xor x1(X1, A, B);
or a4(A4, A1, A2);
or a5(COUT, A3, A4);
xor x2(SUM, X1, CIN);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

行為模式的二位元多工器

module top;
  integer ia,ib,is,ic,id;
  reg  a,b,s,c,d;
  wire out0,out1;

  mux2_behavioral mux2(out0, out1,a,c,b,d,s);

  initial
    begin
      for (is=0; is<=1; is = is + 1)
        begin
          s = is;
          for (ia=0; ia<=1; ia = ia+1)
            begin
              a = ia;
              for (ib=0; ib<=1; ib = ib + 1)
                begin
                  b = ib;
                 begin
                   for (ic=0; ic<=1; ic = ic+1)
                     begin
                       c = ic;
                       for (id=0; id<=1; id = id + 1)
                         begin
                           d = id;
                             #100 $display("a=%d b=%d c=%d d=%d s=%d   out0=%d out1=%d",a,b,c,d,s,out0,out1);
                           
                           end
                         end
                       end
                     end
                   end
                 end
               end

endmodule


module mux2_behavioral(OUT1, OUT2, A0, A1, B0, B1, SEL);
 output OUT1, OUT2;
 input A0, A1, B0, B1, SEL;
 wire  A0, A1, B0, B1, SEL;
 reg   OUT1, OUT2;
 always @(A1 or B1 or SEL)
  OUT2 = (A1 & SEL)|(B1 & ~SEL );
 always @(A0 or B0 or SEL)
  OUT1 = (A0 & SEL)|(B0 & ~SEL );
endmodule

行為模式的1位元多工器

module top;
  integer ia,ib,is;
  reg  a,b,s;
  wire out;

  mux_behavioral mux1(out,a,b,s);

  initial
    begin
      for (is=0; is<=1; is = is + 1)
        begin
          s = is;
          for (ia=0; ia<=1; ia = ia+1)
            begin
              a = ia;
              for (ib=0; ib<=1; ib = ib + 1)
                begin
                  b = ib;
                 #120 $display("a=%d b=%d s=%d   out=%d",a,b,s,out);
               end
            end
        end
    end
endmodule

module mux_behavioral(OUT, A, B, SEL);
 output OUT;
 input A,B,SEL;
 wire  A,B,SEL;
 reg    OUT;

  always @(A or B or SEL)
   OUT = (A & SEL)|(B & ~SEL );
endmodule