1216t

module top;

wire A, B, C, D, Y1, Y2, Y3, Y4, NY, Y, NA, NB, NC, ND;
system_clock #1600 clock1(A);
system_clock #800 clock2(B);
system_clock #400 clock3(C);
system_clock #200 clock4(D);

nor n1(NA, A, A);
nor n2(NB, B, B);
nor n3(NC, C, C);
nor n4(ND, D, D);
nor o1(Y1, A, B, D);
nor o2(Y2, A, NB, NC);
nor o3(Y3, NA, B, NC);
nor o4(Y4, NC, D);
nor o5(NY, Y1, Y2, Y3, Y4);
nor o6(Y, NY, NY);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>2000)$stop;

endmodule

1202測驗

module top;

wire A, B, C, D, NA, NB, NC, ND, F1, F2, F3, F4, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);
nand n1(NA, A, A);
nand n2(NB, B, B);
nand n3(NC, C, C);
nand n4(ND, D, D);
nand a1(F4, A ,NC , ND);
nand a2(F2, NA, NB, D);
nand a3(F3, B, NC, ND);
nand a4(F1, C, D);
nand r1(F, F4, F2, F3, F1);



endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

1202測驗

module top;

wire A, B, C, D, NA, NB, NC, ND, NF, F1, F2, F3, F4, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);

nor a1(NA, A, A);
nor a2(NB, B, B);
nor a3(NC, C, C);
nor a4(ND, D, D);
nor r1(F1,NC,ND);
nor r2(F2,A,B,ND);
nor r3(F3,NB,C,D);
nor r4(F4,NA,C,D);
nor r5(NF,F1,F2,F3,F4);
nor r6(F,NF,NF);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

測驗題目

module top;

wire A, B, C, D, NA, NB, NC, ND, F1, F2, F3, F4, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);
not n1(NA, A);
not n2(NB, B);
not n3(NC, C);
not n4(ND, D);
and a1(F4, A ,NC , ND);
and a2(F2, NA, NB, D);
and a3(F3, B, NC, ND);
and a4(F1, C, D);
or r1(F, F4, F2, F3, F1);



endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

三位元全加器(行為模式)

module fulladder (c_out, sum, a, b, c_in);
wire s1, c1, c2;
output c_out;
output sum;
input a, b, c_in;

assign{c_out,sum}=a+b+c_in;
endmodule

module adder3( c_out, sum, a,  b, c_in);
wire [2:0] c;
output [2:0] sum;
output c_out;
input [2:0] a;
input [2:0] b;
input c_in;

fulladder fa1(c[1], sum[0], a[0], b[0], c_in) ;
fulladder fa2(c[2], sum[1], a[1], b[1], c[1]) ;
fulladder fa3(c_out, sum[2], a[2],b[2], c[2]) ;


endmodule

module main;
reg [2:0] a;
reg [2:0] b;
wire [2:0] sum;
wire c_out;

adder3 DUT (c_out, sum, a, b, 1'b0);

initial
begin
  a = 3'b111;
  b = 3'b000;
end

always #50 begin
  b=b+1;
  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);
end

initial #2000 $finish;

endmodule

三位元全加器(結構模式)

module fulladder (c_out, sum, a, b, c_in);
wire s1, c1, c2;
output c_out;
output sum;

xor g1(s1, a, b);
xor g2(sum, s1, c_in);
and g3(c1, a,b);
and g4(c2, s1, c_in) ;
xor g5(c_out, c2, c1) ;

endmodule

module adder3( c_out, sum, a,  b, c_in);
wire [2:0] c;
output [2:0] sum;
output c_out;
input [2:0] a;
input [2:0] b;
input c_in;

fulladder fa1(c[1], sum[0], a[0], b[0], c_in) ;
fulladder fa2(c[2], sum[1], a[1], b[1], c[1]) ;
fulladder fa3(c_out, sum[2], a[2],b[2], c[2]) ;


endmodule

module main;
reg [2:0] a;
reg [2:0] b;
wire [2:0] sum;
wire c_out;

adder3 DUT (c_out, sum, a, b, 1'b0);

initial
begin
  a = 3'b111;
  b = 3'b000;
end

always #50 begin
  b=b+1;
  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);
end

initial #2000 $finish;

endmodule

一位元全加器(行為模式)

module test_adder1;

 reg a,b;
 reg carry_in ;
 wire sum;
 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial
  begin

    carry_in = 0; a = 0; b = 0;
    # 100 if ( carry_in != 0 | sum !== 0)
                $display(" 0+0+0=00 sum is WRONG!");
              else
                $display(" 0+0+0=00 sum is RIGHT!");
    carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_in != 0 | sum !== 1)
               $display(" 0+0+1=01 sum is WRONG!");
              else
               $display(" 0+0+1=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 0;
    # 100 if ( carry_in != 0 | sum !== 1)
               $display(" 0+1+0=01 sum is WRONG!");
              else
               $display(" 0+1+0=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 1;
    # 100 if ( carry_in != 0 | sum !== 1)
               $display(" 0+1+1=10 sum is WRONG!");
              else
               $display(" 0+1+1=10 sum is RIGHT!");
    carry_in = 1; a = 0; b = 0;
    # 100 if ( carry_in != 0 | sum !== 1)
               $display(" 1+0+0=01 sum is WRONG!");
              else
               $display(" 1+0+0=01 sum is RIGHT!");
    carry_in = 1; a = 0; b = 1;
    # 100 if ( carry_in != 0 | sum !== 1)
               $display(" 1+0+1=10 sum is WRONG!");
              else
               $display(" 1+0+1=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_in != 0 | sum !== 1)
               $display(" 1+1+0=10 sum is WRONG!");
              else
               $display(" 1+1+0=10 sum is RIGHT!");

    carry_in = 1; a = 1; b = 1;
    # 100 if ( carry_in != 1 | sum !== 1)
               $display(" 1+1+1=11 sum is WRONG!");
              else
               $display(" 1+1+1=11 sum is RIGHT!");
    $finish;
  end
endmodule



module adder1_behavorial (carry_out, sum, a, b, carry_in);
 input a, b, carry_in;
 output carry_out, sum;
  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);
  assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule