測驗題目

module top;

wire A, B, C, D, NA, NB, NC, ND, F1, F2, F3, F4, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);
not n1(NA, A);
not n2(NB, B);
not n3(NC, C);
not n4(ND, D);
and a1(F4, A ,NC , ND);
and a2(F2, NA, NB, D);
and a3(F3, B, NC, ND);
and a4(F1, C, D);
or r1(F, F4, F2, F3, F1);



endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule