1216t

module top;

wire A, B, C, D, Y1, Y2, Y3, Y4, NY, Y, NA, NB, NC, ND;
system_clock #1600 clock1(A);
system_clock #800 clock2(B);
system_clock #400 clock3(C);
system_clock #200 clock4(D);

nor n1(NA, A, A);
nor n2(NB, B, B);
nor n3(NC, C, C);
nor n4(ND, D, D);
nor o1(Y1, A, B, D);
nor o2(Y2, A, NB, NC);
nor o3(Y3, NA, B, NC);
nor o4(Y4, NC, D);
nor o5(NY, Y1, Y2, Y3, Y4);
nor o6(Y, NY, NY);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>2000)$stop;

endmodule