1216t

module top;

wire A, B, C, D, Y1, Y2, Y3, Y4, NY, Y, NA, NB, NC, ND;
system_clock #1600 clock1(A);
system_clock #800 clock2(B);
system_clock #400 clock3(C);
system_clock #200 clock4(D);

nor n1(NA, A, A);
nor n2(NB, B, B);
nor n3(NC, C, C);
nor n4(ND, D, D);
nor o1(Y1, A, B, D);
nor o2(Y2, A, NB, NC);
nor o3(Y3, NA, B, NC);
nor o4(Y4, NC, D);
nor o5(NY, Y1, Y2, Y3, Y4);
nor o6(Y, NY, NY);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>2000)$stop;

endmodule

1202測驗

module top;

wire A, B, C, D, NA, NB, NC, ND, F1, F2, F3, F4, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);
nand n1(NA, A, A);
nand n2(NB, B, B);
nand n3(NC, C, C);
nand n4(ND, D, D);
nand a1(F4, A ,NC , ND);
nand a2(F2, NA, NB, D);
nand a3(F3, B, NC, ND);
nand a4(F1, C, D);
nand r1(F, F4, F2, F3, F1);



endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

1202測驗

module top;

wire A, B, C, D, NA, NB, NC, ND, NF, F1, F2, F3, F4, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);

nor a1(NA, A, A);
nor a2(NB, B, B);
nor a3(NC, C, C);
nor a4(ND, D, D);
nor r1(F1,NC,ND);
nor r2(F2,A,B,ND);
nor r3(F3,NB,C,D);
nor r4(F4,NA,C,D);
nor r5(NF,F1,F2,F3,F4);
nor r6(F,NF,NF);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

測驗題目

module top;

wire A, B, C, D, NA, NB, NC, ND, F1, F2, F3, F4, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);
not n1(NA, A);
not n2(NB, B);
not n3(NC, C);
not n4(ND, D);
and a1(F4, A ,NC , ND);
and a2(F2, NA, NB, D);
and a3(F3, B, NC, ND);
and a4(F1, C, D);
or r1(F, F4, F2, F3, F1);



endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule