2個1位元多工器組成1個2位元多工器

module top;
wire OUT0, OUT1, A0, A1, B;
wire  SEL;
system_clock #800 clock1(A0);
system_clock #400 clock2(A1);

system_clock #200 clock5(B0);
system_clock #100 clock6(B1);

system_clock #1600 clock9(SEL);

mux m1(OUT0, A0, B0, SEL);
mux m2(OUT1, A1, B1, SEL);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>2000)$stop;
endmodule

module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule

2個2位元多工器組成4位元多工器

module top;
wire [3:0]OUT, A, B;
wire  SEL;
system_clock #12800 clock1(A[0]);
system_clock #6400 clock2(A[1]);
system_clock #3200 clock3(A[2]);
system_clock #1600 clock4(A[3]);
system_clock #800 clock5(B[0]);
system_clock #400 clock6(B[1]);
system_clock #200 clock7(B[2]);
system_clock #100 clock8(B[3]);
system_clock #25600 clock9(SEL);

mux2 a1(OUT[1:0], A[1:0], B[1:0],SEL);
mux2 a2(OUT[3:2], A[3:2], B[3:2], SEL);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>30000)$stop;
endmodule

module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule

module mux2(OUT, A, B, SEL);
output [1:0] OUT;
input [1:0] A,B;
input SEL;
mux hi (OUT[1], A[1], B[1], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule

1個2位元多工器與1個1位元多工器組合成3位元多工器

module top;
wire [2:0]OUT, A, B;
wire  SEL;
system_clock #3200 clock1(A[0]);
system_clock #1600 clock2(A[1]);
system_clock #800 clock3(A[2]);
system_clock #400 clock4(B[0]);
system_clock #200 clock5(B[1]);
system_clock #100 clock6(B[2]);
system_clock #6400 clock7(SEL);

mux a1(OUT[0], A[0], B[0],SEL);
mux2 a2(OUT[2:1], A[2:1], B[2:1], SEL);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>7000)$stop;
endmodule

module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule

module mux2(OUT, A, B, SEL);
output [1:0] OUT;
input [1:0] A,B;
input SEL;
mux hi (OUT[1], A[1], B[1], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule

3位元多工器(2)

module top;

wire A0, A1, A2, B0, B1, B2, SEL, OUT1, OUT2, OUT3;
system_clock #200 clock1(A0);
system_clock #100 clock2(B0);
system_clock #800 clock1(A1);
system_clock #400 clock2(B1);
system_clock #3200 clock2(A2);
system_clock #1600 clock2(B2);
system_clock #6400 clock1(SEL);
mux m1 (OUT1, A0, B0, SEL);
mux m2 (OUT2, A1, B1, SEL);
mux m3 (OUT3, A2, B2, SEL);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>7000)$stop;

endmodule

module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule

3位元多工器

module top;

wire A0, A1, A2, B0, B1, B2, NSEL, SEL, OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUT8, OUT9;
system_clock #200 clock1(A0);
system_clock #100 clock2(B0);
system_clock #800 clock1(A1);
system_clock #400 clock2(B1);
system_clock #3200 clock2(A2);
system_clock #1600 clock2(B2);
system_clock #6400 clock1(SEL);
not b1(NSEL, SEL);
and a1(OUT1, A1, SEL);
and a2(OUT2, B1, NSEL);
or a5(OUT6, OUT1, OUT2);

and a3(OUT3, A0, SEL);
and a7(OUT7, A2, SEL);

and a4(OUT4, B0, NSEL);
and a8(OUT8, B2, NSEL);

or a6(OUT5, OUT3, OUT4);
or a6(OUT9, OUT7, OUT8);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>7000)$stop;

endmodule

2位元多工器

module top;

wire A0, A1, B0, B1, NSEL, SEL, OUT1, OUT2, OUT3, OUT4, OUT5,OUT6;
system_clock #200 clock1(A0);
system_clock #100 clock2(B0);
system_clock #200 clock1(A1);
system_clock #100 clock2(B1);
system_clock #400 clock1(SEL);




and a1(OUT1, A1, SEL);
and a3(OUT3, A0, SEL);
not b1(NSEL, SEL);

and a2(OUT2, B1, NSEL);
and a4(OUT4, B0, NSEL);
or a5(OUT5, OUT1, OUT2);
or a6(OUT6, OUT3, OUT4);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

4對1多工器

module top;

wire A0, A1, B0, B1, NSEL, SEL, OUT1, OUT2, OUT3, OUT4, OUT5,OUT6,OUT7,OUT8,OUT9,S2,NS2;
system_clock #200 clock1(A0);
system_clock #100 clock2(B0);
system_clock #200 clock1(A1);
system_clock #100 clock2(B1);
system_clock #400 clock1(SEL);
system_clock #800 clock1(S2);



and a1(OUT1, A1, SEL);
and a3(OUT3, A0, SEL);
not b1(NSEL, SEL);
not b2(NS2, S2);
and a2(OUT2, B1, NSEL);
and a4(OUT4, B0, NSEL);
or a5(OUT5, OUT1, OUT2);
or a6(OUT6, OUT3, OUT4);
and a7(OUT7, OUT5, S2);
and a8(OUT8, OUT6, NS2);
or a9(OUT9, OUT7, OUT8);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>2000)$stop;

endmodule

多工器

多工器

10/07 作業

這次比較複雜
module top;

wire A, B, C, D, E, OUT1, OUT2, OUT3, OUT4, OUT5;
system_clock #1600 clock1(A);
system_clock #800 clock2(B);
system_clock #400 clock2(C);
system_clock #200 clock2(D);
system_clock #100 clock2(E);

not a1(OUT1, A);
and a2(OUT2, OUT1, B);
nor a3(OUT3, C, D);
and a4(OUT4, OUT3, E);
or a5(OUT5, OUT2, OUT4);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>3200)$stop;

endmodule