2個1位元多工器組成1個2位元多工器

module top;
wire OUT0, OUT1, A0, A1, B;
wire  SEL;
system_clock #800 clock1(A0);
system_clock #400 clock2(A1);

system_clock #200 clock5(B0);
system_clock #100 clock6(B1);

system_clock #1600 clock9(SEL);

mux m1(OUT0, A0, B0, SEL);
mux m2(OUT1, A1, B1, SEL);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>2000)$stop;
endmodule

module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule