4對1多工器

module top;

wire A0, A1, B0, B1, NSEL, SEL, OUT1, OUT2, OUT3, OUT4, OUT5,OUT6,OUT7,OUT8,OUT9,S2,NS2;
system_clock #200 clock1(A0);
system_clock #100 clock2(B0);
system_clock #200 clock1(A1);
system_clock #100 clock2(B1);
system_clock #400 clock1(SEL);
system_clock #800 clock1(S2);



and a1(OUT1, A1, SEL);
and a3(OUT3, A0, SEL);
not b1(NSEL, SEL);
not b2(NS2, S2);
and a2(OUT2, B1, NSEL);
and a4(OUT4, B0, NSEL);
or a5(OUT5, OUT1, OUT2);
or a6(OUT6, OUT3, OUT4);
and a7(OUT7, OUT5, S2);
and a8(OUT8, OUT6, NS2);
or a9(OUT9, OUT7, OUT8);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>2000)$stop;

endmodule