3位元多工器(2)

module top;

wire A0, A1, A2, B0, B1, B2, SEL, OUT1, OUT2, OUT3;
system_clock #200 clock1(A0);
system_clock #100 clock2(B0);
system_clock #800 clock1(A1);
system_clock #400 clock2(B1);
system_clock #3200 clock2(A2);
system_clock #1600 clock2(B2);
system_clock #6400 clock1(SEL);
mux m1 (OUT1, A0, B0, SEL);
mux m2 (OUT2, A1, B1, SEL);
mux m3 (OUT3, A2, B2, SEL);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>7000)$stop;

endmodule

module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule