wire s1, c1, c2;
output c_out;
output sum;
input a, b, c_in;
assign{c_out,sum}=a+b+c_in;
endmodule
module adder3( c_out, sum, a, b, c_in);
wire [2:0] c;
output [2:0] sum;
output c_out;
input [2:0] a;
input [2:0] b;
input c_in;
fulladder fa1(c[1], sum[0], a[0], b[0], c_in) ;
fulladder fa2(c[2], sum[1], a[1], b[1], c[1]) ;
fulladder fa3(c_out, sum[2], a[2],b[2], c[2]) ;
endmodule
module main;
reg [2:0] a;
reg [2:0] b;
wire [2:0] sum;
wire c_out;
adder3 DUT (c_out, sum, a, b, 1'b0);
initial
begin
a = 3'b111;
b = 3'b000;
end
always #50 begin
b=b+1;
$monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);
end
initial #2000 $finish;
endmodule

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