integer ia,ib,is,ic,id;
reg a,b,s,c,d;
wire out0,out1;
mux2_behavioral mux2(out0, out1,a,c,b,d,s);
initial
begin
for (is=0; is<=1; is = is + 1)
begin
s = is;
for (ia=0; ia<=1; ia = ia+1)
begin
a = ia;
for (ib=0; ib<=1; ib = ib + 1)
begin
b = ib;
begin
for (ic=0; ic<=1; ic = ic+1)
begin
c = ic;
for (id=0; id<=1; id = id + 1)
begin
d = id;
#100 $display("a=%d b=%d c=%d d=%d s=%d out0=%d out1=%d",a,b,c,d,s,out0,out1);
end
end
end
end
end
end
end
endmodule
module mux2_behavioral(OUT1, OUT2, A0, A1, B0, B1, SEL);
output OUT1, OUT2;
input A0, A1, B0, B1, SEL;
wire A0, A1, B0, B1, SEL;
reg OUT1, OUT2;
always @(A1 or B1 or SEL)
OUT2 = (A1 & SEL)|(B1 & ~SEL );
always @(A0 or B0 or SEL)
OUT1 = (A0 & SEL)|(B0 & ~SEL );
endmodule
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