1位元全加器(結構模式)

module top;

wire A, B, CIN, COUT, SUM, A1, A2, A3, A4, X1;
system_clock #400 clock1(A);
system_clock #200 clock2(B);
system_clock #800 clock2(CIN);
and a3(A3, A, CIN);
and a2(A2, CIN, B);
and a1(A1, A, B);
xor x1(X1, A, B);
or a4(A4, A1, A2);
or a5(COUT, A3, A4);
xor x2(SUM, X1, CIN);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule