小小改變2

經過今天的學習，我覺得Verilog是很有趣的，隨著漸漸搞懂它，我漸漸喜歡上她了。
module top;

wire A, B, C, D, OUT1, OUT2, OUT3;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);

and a1(OUT1, A, B);
and a2(OUT2, C, D);
or  a3(OUT3, OUT1, OUT2);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule